The present invention relates generally to chip packaging and methods of packaging and, more particularly, to compact packaging of chips and methods thereof in electronic environments that minimize undesired electronic effects, promote speed, and enhance packaging versatility.
Packaging and operational concerns of computer chip systems are becoming problematic given their higher operating speeds, higher power requirements as well as the ever increasing demands for their miniaturization and the additional system functionalities being added. Consequently, electromagnetic interference (EMI) and signal integrity (SI) concerns associated with the foregoing issues are similarly difficult to address. Moreover, further EMI and SI concerns arise given that the electronic devices in which such chip systems are used are also being driven by board level compactness considerations. Accordingly, achieving higher speeds, electromagnetic compatibility (EMC) and SI, for such chips and electronic devices are of critical importance from commercial considerations.
In many situations, chip modules or packages are mounted on a printed circuit board and connected by lead frames to a variety of devices including passive devices of the kind typically associated with such chip modules. EMI is a problem because of, for example, the inductance generally associated with the relatively large area encompassed by long lead frames extending between the chip module and the surrounding passive devices on the printed circuit board. Moreover, the printed circuit board space or real estate is consumed because these passive devices generally surround and are spaced from the chip module's periphery thereby hindering miniaturization.
A known approach for addressing this situation is the use of chip-scale packaging technology wherein electronic components are permanently stacked on a chip and permanently retained within a module housing. While this approach has many advantages, it does not allow for customizing and modifying the components that are permanently attached to the chip. Accordingly, known chip packaging technologies and chip-scale packaging approaches are less versatile in that they do not enable opportunities for customizing and changing components associated with a chip. Moreover, these chip-scale packaging approaches do not allow external testing and power supply connectors to be electrically coupled to the chip modules.
Without the ability to provide semiconductor devices with enhanced power and speed functionalities especially in a compact environment so as to minimize EMI and enhance SI, the true potential of these devices is less than otherwise attainable. Furthermore, without the ability to allow the customization or modification of such semiconductor devices in the field, their true potential is diminished.